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R8C/12 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0068-0120 Rev.1.20 Jan 27, 2006
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed. The data flash ROM (2 KB X 2 blocks) is embedded.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
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R8C/12 Group
1. Overview
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic instructions 89 instructions Minimum instruction execution time 62.5 ns (f(XIN) = 16 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2 "Product List" Peripheral Port Input/Output: 22 (including LED drive port), Input: 2 function LED drive port I/O port: 8 Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture circuit) Serial Interface *1 channel Clock synchronous, UART *1 channel UART A/D converter 10-bit A/D converter: 1 circuit, 8 channels Watchdog timer 15 bits x 1 (with prescaler) Reset start function selectable Interrupt Internal: 9 factors, External: 5 factors, Software: 4 factors, Priority level: 7 levels Clock generation circuit 2 circuits *Main clock generation circuit (Equipped with a built-in feedback resistor) *On-chip oscillator Oscillation stop detection function Main clock oscillation stop detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 16 MHZ) characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ) Power consumption Typ.8mA (VCC = 5.0 V (f(XIN) = 16 MHZ) Typ.5mA (VCC = 3.0 V, (f(XIN) = 10 MHZ) Typ.35A (VCC = 3.0 V, Wait mode, peripheral clock stops) Typ.0.7A (VCC = 3.0 V, Stop mode) Flash memory Program/erase supply voltage VCC = 2.7 to 5.5 V Program/erase endurance 10,000 times (Data flash) 1,000 times (Program ROM) Operating ambient temperature -20 to 85 C -40 to 85 C (D-version) Package 32-pin plastic mold LQFP
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R8C/12 Group
1. Overview
1.3 Block Diagram
Figure 1.1. shows this MCU block diagram.
8
8
5
1
2
I/O port
Port P0
Port P1
Port P3
Port P4
Peripheral functions
Timer A/D converter (10 bits 8 channels) System clock generator UART or Clock synchronous serial I/O (8 bits 1 channel) UART (8 bits 1 channel) XIN-XOUT On-chip oscillator
Timer X (8 bits) Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits)
R8C/Tiny Series CPU core
Watchdog timer (15 bits)
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM
(1)
RAM
(2)
Multiplier
NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type.
Figure 1.1 Block Diagram
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R8C/12 Group
1. Overview
1.4 Product Information
Table 1.2 lists the product information. Table 1.2 Product Information
Type No. R5F21122FP R5F21123FP R5F21124FP R5F21122DFP R5F21123DFP R5F21124DFP ROM capacity
Program ROM Data flash
As of January 2006 RAM capacity 512 bytes 768 bytes 1K bytes 512 bytes 768 bytes 1K bytes Package type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A D version Remarks Flash memory version
8K bytes 12K bytes 16K bytes 8K bytes 12K bytes 16K bytes
2K bytes x 2 2K bytes x 2 2K bytes x 2 2K bytes x 2 2K bytes x 2 2K bytes x 2
Type No. R 5 F
21 12 4 D FP
Package type: FP : PLQP0032GB-A
Classification: D: Operating ambient temperature -40 C to 85 C No symbol: Operating ambient temperature -20 C to 85 C ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/12 group
R8C/Tiny series
Memory type: F: Flash memory version
Renesas MCU Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
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1. Overview
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
P30/CNTR0 AVSS P31/TZOUT AVCC/VREF P32/INT2/CNTR1
24 23 22 21 20 19 18 17 P06/AN1 P05/AN2 P04/AN3 MODE P03/AN4 P02/AN5 P01/AN6 P00/AN7/TxD11 25 26 27 28 29 30 31 32 12345678 16 15 14 R8C/12 Group 13 12 11 10 9 P45/INT0 P10/KI0 P11/KI1 P12/KI2 P13/KI3 P14/TxD0 P15/RxD0 P16/CLK0
P07/AN0 IVCC (3)
NOTES: 1. P47 functions only as an input port. 2. When using on-chip debugger, do not use p P00/AN7/TxD11 and P37/TxD10/RxD1. 3. Do not connect IVcc to Vcc.
Figure 1.3 Pin Configuration (Top View)
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RESET XOUT/P47 (1) VSS XIN/P46 VCC P17/INT1/CNTR0
P37/TxD10/RxD1 CNVSS
Package: PLQP0032GB-A (32P6U-A)
P33/INT3/TCIN
R8C/12 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description Table 1.3 Pin description Signal name Power supply input IVcc Pin name Vcc, Vss IVcc I/O type I O Function Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. This pin is to stabilize internal power supply. Connect this pin to Vss via a capacitor (0.1 F). Do not connect to Vcc. Power supply input pins for A/D converter. Connect the AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. Input "L" on this pin resets the MCU. Connect this pin to Vss via a resistor. Connect this pin to Vcc via a resistor. These pins are provided for the main clock generating circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. ______ INT interrupt input pins. Key input interrupt pins. Timer X I/O pin Timer X output pin Timer Y I/O pin Timer Z output pin Timer C input pin Transfer clock I/O pin. Serial data input pins. Serial data output pins. Reference voltage input pin for A/sD converter. Connect the VREF pin to Vcc. Analog input pins for A/D converter These are 8-bit CMOS I/O ports. Each port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pullup resistor or not by program. P10 to P17 also function as LED drive ports. Port for input-only.
Analog power supply input Reset input CNVss MODE Main clock input
AVcc, AVss
___________
I
RESET CNVss MODE XIN
I I I I O
_______
Main clock output XOUT
_____ _______
INT interrupt input INT0 to INT3 _____ _____ Key input interrupt KI0 to KI3 Timer X CNTR0 __________ CNTR0 Timer Y CNTR1 Timer Z TZOUT Timer C TCIN Serial interface CLK0 RxD0, RxD1 TxD0, TxD10, TxD11 Reference voltage VREF input A/D converter AN0 to AN7 I/O port P00 to P07, P10 to P17, P30 to P33, P37, P45
I I I/O O I/O O I I/O I O I I I/O
Input port
P46, P47
I
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R8C/12 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
b31
b15
b8 b7
b0
R2 R3
R0H(high-order of R0) R0L(low-order of R0) R1H(high-order of R1) R1L(low-order of R1)
R2 R3 A0 A1 FB
Data registers(1)
Address registers(1) Frame base registers(1)
b0
b19
b15
INTBH
INTBL
Interrupt table register
The 4-high order bits of INTB are INTBH and the 16-low bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
UI
OB S Z DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTES: 1. A register bank comprises these registers. Two sets of register banks are provided
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
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2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit. 2.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.8.3 Zero Flag (Z) The Z flag is set to "1" when an arithmetic operation resulted in 0; otherwise, "0". 2.8.4 Sign Flag (S) The S flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, "0". 2.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is "0". The register bank 1 is selected when this flag is set to "1". 2.8.6 Overflow Flag (O) The O flag is set to "1" when the operation resulted in an overflow; otherwise, "0". 2.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0", and are enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0", USP is selected when the U flag is set to "1". The U flag is set to "0" when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit When write to this bit, set to "0". When read, its content is indeterminate.
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R8C/12 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses from 0200016 to 02FFF16. The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing data, but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function control registers are located them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
0000016 SFR
(See Chapter 4 for details.)
002FF16
0040016 Internal RAM 0XXXX16 0200016 Internal ROM (data flash)(1) 02FFF16 0FFDC16 Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer*Oscillation stop detection
0YYYY16 Internal ROM (program ROM) 0FFFF16 Expansion area FFFFF16
0FFFF16
(Reserved) (Reserved) Reset
NOTES: 1. The data flash block A (2K bytes) and block B (2K bytes) are shown. 2. Blank space are reserved. No access is allowed.
Type name
R5F21124FP, R5F21124DFP R5F21123FP, R5F21123DFP R5F21122FP, R5F21122DFP
Internal ROM Address 0YYYY16 Size
16K bytes 12K bytes 8K bytes 0C00016 0D00016 0E00016
Internal RAM Address 0XXXX16 Size
1K bytes 768 bytes 512 bytes 007FF16 006FF16 005FF16
Figure 3.1 Memory Map
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R8C/12 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information(1)(1)
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol
After reset
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer reset register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
PM0 PM1 CM0 CM1 AIER PRCR OCD WDTR WDTS WDC RMAD0
XXXX0X002 00XXX0X02 011010002 001000002 XXXXXX002 00XXX0002 000001002 XX16 XX16 000111112 0016 0016 X016 0016 0016 X016
Address match interrupt register 1
RMAD1
INT0 input filter select register
INT0F
XXXXX0002
NOTES : 1. Blank spaces are reserved. No access is allowed. X : Undefined
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4. Special Function Register (SFR)
Table 4.2 SFR Information(2)(1)
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register
Symbol
After reset
Key input interrupt control register AD conversion interrupt control register
KUPIC ADIC
XXXXX0002 XXXXX0002
UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register
INT2 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register INT1 interrupt control register INT3 interrupt control register Timer C interrupt control register INT0 interrupt control register
S0TIC S0RIC S1TIC S1RIC INT2IC TXIC TYIC TZIC INT1IC INT3IC TCIC INT0IC
XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002
NOTES : 1. Blank spaces are reserved. No access is allowed. X : Undefined
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4. Special Function Register (SFR)
Table 4.3 SFR Information(3)(1)
Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Register Timer Y, Z mode register Prescaler Y register Timer Y secondary register Timer Y primary register Timer Y, Z waveform output control register Prescaler Z register Timer Z secondary register Timer Z primary register
Symbol TYZMR PREY TYSC TYPR PUM PREZ TZSC TZPR
After reset 0016 FF16 FF16 FF16 0016 FF16 FF16 FF16
Timer Y, Z output control register Timer X mode register Prescaler X register Timer X register Timer count source setting register Timer C register
TYZOC TXMR PREX TX TCSS TC
0016 0016 FF16 FF16 0016 0016 0016
External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Capture register
INTEN KIEN TCC0 TCC1 TM0
0016 0016 0016 0016 0016 0016
UART0 transmit/receive mode register
UART0 bit rate register UART0 transmit buffer register
UART0 transmit/receive control register 0 UART0 transmit/receive control register 1
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator UART1 transmit buffer register
UART1 transmit/receive control register 0 UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016
NOTES : 1. Blank spaces are reserved. No access is allowed. X : Undefined
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4. Special Function Register (SFR)
Table 4.4 SFR Information(4)(1)
Address
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Register AD register
Symbol AD
After reset XXXXXXXX2 XXXXXXXX2
AD control register 2 AD control register 0 AD control register 1
ADCON2 ADCON0 ADCON1
0016 00000XXX2 0016
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P3 register Port P3 direction register Port P4 register Port P4 direction register
P0 P1 PD0 PD1 P3 PD3 P4 PD4
XX16 XX16 0016 0016 XX16 0016 XX16 0016
Pull-up control register 0 Pull-up control register 1 Port P1 drive capacity control register
PUR0 PUR1 DRR
00XX00002 XXXXXX0X2 0016
01B316 01B416 01B516 01B616 01B716
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 Option function select register (2)
FMR4 FMR1 FMR0 OFS
010000002 1000000X2 000000012
(Note 2)
0FFFF16
NOTES : 1. Blank columns, 010016 to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed. 2. The watchdog timer control bit is assigned. Refer to "Figure11.2 OFS, WDC, WDTR and WDTS registers" for the OFS register details X : Undefined
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R8C/12 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Symbol
VCC AVCC VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr=25 C
Parameter
Condition
VCC=AVCC VCC=AVCC
Rated value
-0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150
Unit
V V V V mW C C
Table 5.2 Recommended Operating Conditions
Symbol
VCC AVcc Vss AVss VIH VIL I OH (sum) I OH (peak) I OH (avg) I OL (sum) I OL (peak)
Parameter
Supply voltage Analog supply voltage Supply voltage Analog supply voltage "H" input voltage "L" input voltage Sum of all pins' IOH "H" peak all output currents (peak) "H" peak output current "H" average output current Sum of all pins' IOL "L" peak all output currents (peak) "L" peak output Except P10 to P17 current P10 to P17 "L" average output current Except P10 to P17 P10 to P17
Conditions
Min.
2.7
Standard Typ.
VCC(3) 0 0
Max.
5.5
Unit
V V V V
0.8VCC 0
VCC 0.2VCC -60.0 -10.0 - 5 .0 60 10
V V mA mA mA mA mA mA mA mA mA mA MHz MHz
Drive ability HIGH Drive ability LOW
30 10 5 15 5 16 10
I OL (avg)
f (XIN)
Drive ability HIGH Drive ability LOW Main clock input oscillation frequency 3.0V Vcc 5.5V 2.7V Vcc < 3.0V
0 0
NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold Vcc=AVcc.
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R8C/12 Group Table 5.3 A/D Conversion Characteristics
Symbol
- - Resolution
5. Electrical Characteristics
Parameter Absolute accuracy
Measuring condition
Vref =VCC
Standard Unit Min. Typ. Max.
10 3 2 5 2 10 3.3 2.8 VCC(4) 0 0.25 1.0 Vref 10 10 40 Bit LSB LSB LSB LSB k s s V V MHz MHz
10 bit mode 8 bit mode 10 bit mode 8 bit mode
oAD=10 MHz, Vref=Vcc=5.0V oAD=10 MHz, Vref=Vcc=5.0V oAD=10 MHz, Vref=Vcc=3.3V(3) oAD=10 MHz, Vref=Vcc=3.3V(3)
tCONV VREF VIA
RLADDER Ladder resistance Conversion time Reference voltage Analog input voltage
VREF=VCC
10 bit mode oAD=10 MHz, Vref=Vcc=5.0V 8 bit mode oAD=10 MHz, Vref=Vcc=5.0V
-
Without sample & hold A/D operating clock frequency(2) With sample & hold
NOTES: 1. VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. If fAD exceeds 10 MHz, divide the fAD and hold A/D operating clock frequency (OAD) 10 MHz or below. 3. If the AVcc is less than 4.2V, divide the fAD and hold A/D operating clock frequency (OAD) fAD/2 or below. 4. Hold Vcc=Vref.
P0 P1 P2 P3 P4 30pF
Figure 5.1 Port P0 to P4 measurement circuit
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R8C/12 Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics
Symbol
- - - td(SR-ES) - - - - - Program/Erase
5. Electrical Characteristics
Parameter
endurance(2)
Measuring condition
Min.
1,000(3)
Standard Typ.
50 0.4
Max
Unit
times s s
Byte program time Block erase time Time delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program, Erase Temperature Data hold time(7) Ambient temperature = 55 C 10 2.7 2.7 0 20
8 5.5 5.5 60
ms ms V V C year
NOTES: 1. VCC=AVcc=2.7 to 5.5V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of Program/Erase The endurance of Program/Erase shows a time for each block. If the program/erase number is "n" (n = 1,000, 10,000), "n" times erase can be performed for each block. For example, if performing one-byte write to the distinct addresses on Block A of 2K-byte block 2048 times and then erasing that block, the number of Program/Erase cycles is one time. However, performing multiple writes to the same address before an erase operation is prohibited (overwriting prohibited). 3. Numbers of Program/Erase cycles for which all electrical characteristics is guaranteed. 4. To reduce the number of Program/Erase cycles, a block erase should ideally be performed after writing in series as many distinct addresses (only one time each) as possible. If programming a set of 16 bytes, write up to 128 sets and then erase them one time. This will result in ideally reducing the number of Program/Erase cycles. Additionally, averaging the number of Program/Erase cycles for Block A and B will be more effective. It is important to track the total number of block erases and restrict the number. 5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error disappears. 6. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/12 Group
5. Electrical Characteristics
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
- - - - - td(SR-ES) - - - - -
Parameter
Program/Erase endurance(2)
Byte program time(program/erase endurance 1000 times) Byte program time(program/erase endurance >1000 times) Block erase time(program/erase endurance 1000 times) Block erase time(program/erase endurance >1000 times)
Measuring condition
Standard Min. Typ.
10000(3) 50 65 0.2 0.3
Max
400
Unit
times s s
9
s s
Time delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program/Erase Temperature Data hold time(9) Ambient temperature = 55 C 10 2.7 2.7 -20(-40)(8) 20
8 5.5 5.5 85
ms ms V V C year
NOTES: 1. Referenced to VCC=AVcc=2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2. Definition of Program/Erase The endurance of Program/Erase shows a time for each block. If the program/erase number is "n" (n = 1,000, 10,000), "n" times erase can be performed for each block. For example, if performing one-byte write to the distinct addresses on Block A of 2K-byte block 2048 times and then erasing that block, the number of Program/Erase cycles is one time. However, performing multiple writes to the same address before an erase operation is prohibited (overwriting prohibited). 3. Numbers of Program/Erase cycles for which all electrical characteristics is guaranteed. 4. Table 16.5 applies for Block A or B when the Program/Erase cycles are more than 1000. The byte program time up to 1000 cycles are the same as that of the program area (see Table 5.4). 5. To reduce the number of Program/Erase cycles, a block erase should ideally be performed after writing in series as many distinct addresses (only one time each) as possible. If programming a set of 16 bytes, write up to 128 sets and then erase them one time. This will result in ideally reducing the number of Program/Erase cycles. Additionally, averaging the number of Program/Erase cycles for Block A and B will be more effective. It is important to track the total number of block erases and restrict the number. 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error disappears. 7. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representa-tive. 8. -40 C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
Erase-suspend request (interrupt request)
FMR46 td(SR-ES)
Figure 5.2 Time delay from Suspend Request until Erase Suspend Table 5.6 Power Circuit Timing Characteristics
Symbol
td(P-R) td(R-S)
Parameter
Time for internal power supply stabilization during powering-on(2) STOP release time(3)
Measuring condition
Min.
1
Standard Typ.
Max.
2000 150
Unit
s s
NOTES: 1. The measuring condition is Vcc=AVcc=2.7 to 5.5 V and Topr=25 C. 2. This shows the waiting time until the internal power supply generating circuit is stabilized during powering-on. 3. This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 17 of 25
R8C/12 Group Table 5.7 Electrical Characteristics (1)
Symbol
"H" output voltage VOH XOUT "L" output voltage VOL Except P10 to P17, XOUT P10 to P17
5. Electrical Characteristics [Vcc=5V]
Measuring condition
IOH=-5mA IOH=-200A Drive capacity HIGH Drive capacity LOW IOL= 5 mA IOL= 200 A Drive capacity HIGH Drive capacity LOW Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW IOL= 15 mA IOL= 5 mA IOL= 200 A IOL= 1 mA IOL=500 A 0 .2 IOH=-1 mA IOH=-500A
Parameter
Except XOUT
Min.
VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0
Standard Typ. Max.
VCC VCC VCC VCC 2.0 0.45 2.0 2.0 0.45 2.0 2.0 1.0
Unit
V V V V V V V V V V V V
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1, P45 RESET
0 .2 VI=5V VI=0V VI=0V 30 40 At stop mode 2 .0 50 1 .0 125
2.2 5.0
V A A k M kHz V
IIH IIL RPULLUP RfXIN fRING-S VRAM
"H" input current "L" input current Pull-up resistance Feedback resistance
Low-speed on-chip oscillator frequency
-5.0
167 250
XIN
RAM retention voltage
NOTES: 1. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=20MHz unless otherwise specified.
Table 5.8 Electrical Characteristics (2)
Symbol Parameter
[Vcc=5V]
Measuring condition
High-speed mode
XIN=16 MHz (square wave) On-chip oscillator on=125 kHz No division XIN=10 MHz (square wave) On-chip oscillator on=125 kHz No division
Min.
Standard Typ.
8
Max.
14
Unit
mA
5
mA
Medium-speed mode ICC Power supply current (VCC=3.3 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS
XIN=16 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 XIN=10 MHz (square wave) On-chip oscillator on=125 kHz Division by 8
3
mA
2
mA
On-chip oscillator mode Wait mode
Main clock off On-chip oscillator on=125 kHz Division by 8 Main clock off On-chip oscillator on=125 kHz When a WAIT instruction is executed(1) Peripheral clock operation Main clock off On-chip oscillator on=125 kHz When a WAIT instruction is executed(1) Peripheral clock off Main clock off, Topr = 25 C On-chip oscillator off CM10="1" Peripheral clock off
470
900
A
40
80
A
Wait mode
38
76
A
Stop mode
0 .8
3.0
A
NOTES: 1. Timer Y is operated with timer mode. 2. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=20MHz unless otherwise specified.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
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R8C/12 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 C) [VCC=5V]
Table 5.9 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter Standard Min. Max. 62.5 - 30 - 30 - Unit ns ns ns
XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width
________
Table 5.10 CNTR0 input, CNTR1 input, INT2 input Symbol Parameter tC(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width
Standard Min. Max. 100 - 40 - 40 -
Unit ns ns ns
________
Table 5.11 TCIN input, INT3 input Symbol
Parameter
tC(TCIN) ns TCIN input cycle time tWH(TCIN) ns TCIN input HIGH pulse width tWL(TCIN) ns TCIN input LOW pulse width NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5). Table 5.12 Serial Interface Symbol tC(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Standard Min. Max. 400(1) - 200(2) - 200(2) -
Unit
Parameter
CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
________
Standard Min. Max. 200 - 100 - 100 - 80 - 0 - 35 - 90 -
Unit ns ns ns ns ns ns ns
Table 5.13 External interrupt INT0 input Symbol Parameter tW(INH) tW(INL)
________
INT0 input HIGH pulse width ________ INT0 input LOW pulse width
Standard Max. Min. 250(1) - 250(2) -
Unit ns ns
NOTES: ________ ________ 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 19 of 25
R8C/12 Group
5. Electrical Characteristics
VCC = 5V
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi tW(INH) tsu(D-C) th(C-D)
Figure 5.3 Vcc=5V timing diagram
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 20 of 25
R8C/12 Group Table 5.14 Electrical Characteristics (3)
Symbol
"H" output voltage VOH "L" output voltage VOL
5. Electrical Characteristics [Vcc=3V]
Measuring condition
IOH=-1mA Drive capacity HIGH Drive capacity LOW IOL= 1 mA Drive capacity HIGH Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW IOL= 2 mA IOL= 1 mA IOL= 0.1 mA IOL=50 A 0 .2 IOH=-0.1 mA IOH=-50 A
Parameter
Except XOUT XOUT Except P10 to P17, XOUT P10 to P17
Min.
VCC-0.5 VCC-0.5 VCC-0.5
Standard Typ. Max.
VCC VCC VCC 0 .5 0 .5 0 .5 0 .5 0 .5 0 .8
Unit
V V V V V V V V V
VT+-VT-
Hysteresis
INTo, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RxD0, RxD1, P45 RESET
0.2 VI=3V VI=0V VI=0V 66 40 At stop mode 2 .0 160 3.0 125
1 .8 4.0
V A A k M kHz V
IIH IIL RPULLUP RfXIN fRING VRAM
"H" input current "L" input current Pull-up resistance Feedback resistance On-chip oscillator frequency RAM retention voltage XIN
-4.0
500 250
NOTES: 1. Referenced to VCC=AVCC=2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=10MHz unless otherwise specified.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 21 of 25
R8C/12 Group Table 5.15 Electrical Characteristics (4)
Symbol Parameter
High-speed mode
5. Electrical Characteristics [Vcc=3V]
Measuring condition
XIN=16 MHz (square wave) On-chip oscillator on=125 kHz No division XIN=10 MHz (square wave) On-chip oscillator on=125 kHz No division
Min.
Standard Typ.
7
Max.
12
Unit
mA
5
mA
Medium-speed mode ICC Power supply current (VCC1=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS
XIN=16 MHz (square wave) On-chip oscillator on=125 kHz Division by 8 XIN=10 MHz (square wave) On-chip oscillator on=125 kHz Division by 8
2 .5
mA
1 .6 420 800
mA
On-chip oscillator mode Wait mode
Main clock off On-chip oscillator on=125 kHz Division by 8 Main clock off On-chip oscillator on=125 kHz When a WAIT instruction is executed(1) Peripheral clock operation Main clock off On-chip oscillator on=125 kHz When a WAIT instruction is executed(1) Peripheral clock off Main clock off, Topr = 25 C On-chip oscillator off CM10="1" Peripheral clock off
A
37
74
A
Wait mode
35
70
A
Stop mode
0 .7
3 .0
A
NOTES: 1. Timer Y is operated with timer mode. 2. Referenced to VCC=AVCC=2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=10MHz unless otherwise specified.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 22 of 25
R8C/12 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 C) [VCC=3V]
Table 5.16 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width
________
Table 5.17 CNTR0 input, CNTR1 input, INT2 input Symbol Parameter tC(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width
Standard Min. Max. 300 - 120 - 120 -
Unit ns ns ns
________
Table 5.18 TCIN input, INT3 input Symbol Parameter Standard Min. Max. 1200(1) - 600(2) - 600(2) - Unit
tC(TCIN) ns TCIN input cycle time tWH(TCIN) ns TCIN input HIGH pulse width tWL(TCIN) ns TCIN input LOW pulse width NOTES: 1. When using the Timer C capture function, adjust the cycle time above ( 1/ Timer C count source frequency x 3). 2. When using the Timer C capture function, adjust the pulse width above ( 1/ Timer C count source frequency x 1.5).
Table 5.19 Serial Interface Symbol tC(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Parameter
CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
Standard Min. Max. 300 - 150 - 150 - 160 - 0 - 55 - 90 -
Unit ns ns ns ns ns ns ns
________
Table 5.20 External interrupt INT0 input Symbol Parameter tW(INH) tW(INL)
________
INT0 input HIGH pulse width ________ INT0 input LOW pulse width
Standard Min. Max. 380(1) - 380(2) -
Unit ns ns
NOTES: ________ ________ 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 23 of 25
R8C/12 Group
5. Electrical Characteristics
VCC = 3V
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi tW(INH) tsu(D-C) th(C-D)
Figure 5.4 Vcc=3V timing diagram
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 24 of 25
R8C/12 Group
Package Dimensions
Package Dimensions
JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g
HD *1
D
24
17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
HE E
25
16
c1
*2
c
Reference Symbol
Dimension in Millimeters
Terminal cross section 32
ZE
9
1 ZD Index mark
8
A2
A
F
A1
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
y e
*3
Detail F bp x
Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0
Rev.1.20 Jan 27, 2006 REJ03B0068-0120
page 25 of 25
c
REVISION HISTORY
Rev. Date Page 0.10 Oct 28, 2003 0.20 Dec05, 2003 16 First edition issued Table 16.5 revised
R8C/12 Group Datasheet
Description Summary
1.00 Sep30, 2004 All pages 2 5 6 9 10-13 12 14 15 16 17 18 19 21 22 23 1.10 Apr.27.2005 4 5 10 12 15 16 17 21 26 2 3 4
Words standardized (on-chip oscillator, serial interface, A/D) Table 1.1 revised Figure 1.3, NOTES 3 added Table 1.3 revised Figure 3.1, NOTES added One body sentence in chapter 4 added ; Titles of Table 4.1 to 4.4 added Table 4.3 revised ; Table 4.4 revised Table 5.2 revised Table 5.3 revised Table 5.4 and 5.5 revised Table 5.7 revised Table 5.8 revised Table 5.13 revised Table 5.14 revised Table 5.15 revised Table 5.17 revised Table 1.2, Figure 1.2 package name revised Figure 1.3 package name revised Table 4.1 revised Table 4.3 revised Table 5.3 partly revised Table 5.4, Table 5.5 partly added Table 5.6, Table 5.7 partly revised Table 5.14 partly revised Package Dimensions revised Table 1.1 Performance outline revised Figure 1.1 Block diagram partly revised 1.4 Product Information, title of Table 1.2 "Product List" "Product Informaton" revised ROM capacity; "Program area" "Program ROM", "Data area" "Data flash" revised Figure 1.2 Type No., Memory Size, and Package partly revised Table 1.3 Pin description revised 2 Central Processing Unit (CPU) revised Figure 2.1 CPU register revised 3 Memory, Figure 3.1 Memory Map; "Program area" "Program ROM", "Data area" "Data flash" revised Table 4.1 SFR Information(1) NOTES:1 revised
1.20 Jan.27.2006
6 7-8 9 10
A-1
REVISION HISTORY
Rev. Date Page 1.20 Jan.27.2006 11 12
R8C/12 Group Datasheet
Description Summary
13 14 15
16
17
18
21 22
Table 4.2 SFR Information(2) NOTES:1 revised Table 4.3 SFR Information(3); 008116: "Prescaler Y" "Prescaler Y Register" 008216: "Timer Y Secondary" "Timer Y Secondary Register" 008316: "Timer Y Primary" "Timer Y Primary Register" 008516: "Prescaler Z" "Prescaler Z Register" 008616: "Timer Z Secondary" "Timer Z Secondary Register" 008716: "Timer Z Primary" "Timer Z Primary Register" 008C16: "Prescaler X" "Prescaler X Register" revised NOTES:1 revised Table 4.4 SFR Information(4) NOTES:1 revised Table 5.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised Table 5.3 A/D Conversion Characteristics; "A/D operation clock frequency" "A/D operating clock frequency" revised NOTES: 1, 2, 3, 4 revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; "Data retention duration" "Data hold time" revised "Topr" "Ambient temperature" NOTES: 1 to 7 added Measuring condition of byte program time and block erase time deleted Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical characteristics "Data retention duration" "Data hold time" revised "Topr" "Ambient temperature" NOTES: 1, 3 revised, NOTES: 9 added Measuring condition of byte program time and block erase time deleted Table 5.7 Electrical Characteristics (1) [VCC=5V]; "P10 to P17 Except XOUT" "Except P10 to P17, XOUT" revised Table 5.8 Electrical Characteristics (2) [VCC=5V]; Measuring condition Stop mode: "Topr = 25 C" added NOTES: 1, 2 revised Table 5.14 Electrical Characteristics (3) [VCC=3V] "P10 to P17 Except XOUT" "Except P10 to P17, XOUT" revised Table 5.15 Electrical Characteristics (4) [VCC=3V]; Measuring condition Stop mode: "Topr = 25 C" added NOTES: 1, 2 revised
A-2
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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